(China (Mainland))
Product Summary
The PEF20525FV1.3 is a 2 Channel Serial Optimized Communication Controller for HDLC/PPP. The serial channels are derived from updated protocol logic of thePEF20525FV1.3 providing a large set of protocol support and variety in serial interface configuration. This allows easy integration to different environments and applications.
Parametrics
PEF20525FV1.3 absolute maximum ratings: (1)Ambient temperature under bias, TA: 0 to 70℃; (2)Storage temperature, Tstg: – 65 to 125℃; (3)IC supply voltage, VDD3: – 0.3 to 3.6 V; (4)Voltage on any signal pin with respect to ground, VS: – 0.4 to 5.5 V; (5)ESD robustness, VESD,HBM: 2000 V.
Features
PEF20525FV1.3 features: (1)On-chip clock generation or external clock sources; (2)On-chip DPLLs for clock recovery; (3)Baud rate generator; (4)Clock gating signals; (5)Clock gapping capability; (6)Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1); (7)NRZ, NRZI, FM and Manchester data encoding; (8)Two independent channels; (9)Full duplex data rates on each channel of up to 12.5 Mbit/s sync - 2 Mbit/s with DPLL; (10)64 Bytes deep receive FIFO per SCC; (11)64 Bytes deep transmit FIFO per SCC.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
|---|---|---|---|---|---|---|---|---|---|---|
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 PEF20525FV1.3 |
Infineon Technologies |
Network Controller & Processor ICs T/E |
Data Sheet |
Negotiable |
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